As the process technology advancing and the complexity of chip increasing, designers are inevitable faced to make choice between functionality verificaiton and physical implementation within a limited resources. eWave provides a high quality engineering resource to assist you on performing labor-intensive layout activities and Place and Route. With leveraging different customer requests, eWave has accumlated plenty of physical implementation experiences. With high efficiency, seamless interface, complete verification flow, we promise to our customer the smallest die area, best timing performance and optimized power dissipation. We have competed a number of multi-million gate count  designs in the past and we will apply proven methodologies, whether  flatten or hierarchical design approach, to ensure on-time delivery.

At nanometer technology node, static power dissipation and cross talk issue can become a significant, or even dominant. Cross talking analysis and power optimization are two major topics in our backend design service flow.

eWave provides floorplaning, including SSO evaluation, IO planning, and early bonding diagram evaluation per customer request.

    
Phase I: Check-in Acceptance
To ensure a smooth design implementation, the first step is verify the correctness of data, which includes library data, technology data, and customer sign-off database. eWave perform pre-layout timing qualification to verify customer netlist and constrain files in order to discover possible concens earlier and then feedback to customer. eWave has a standard procedure of check-in acceptance cover a variety of different databases to check the crossing consistence.

Phase II: Design Closing
The major design change occurs after synthesizing design, which involves inserting memory BIST, scans chains insertion, IP/Macro instantiation,
IO/Power pads adding. eWave performs
1. Design for test
2. Floorplaning,
3. SSO noise optimization,
4. Timing optimzation,
5. Power optimzation,
6. Power pad and power ring optimization,
7. Logic equivalence cheching

Phase III: Physical Implementation
A sequence of actions is conducted to complete top level implementation:
Design Setup, Floorplan, Placement, CTS, Routing, Timing Optimization, LVS and DRC clean up, power optimization, SI prevention, double-cut vias, and dummy metal insertion

Phase IV: Chip Sign-off
The final chip finishing process consists of bring detailed information for full chip extraction, power, and timing. Integrated all created physical layouts, perform final logic equivalence checker, transistor level LVS and DRC verification, run post layout simulation if necessary, check bonding diagram, and prepare the design for tape-out.