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Turnkey Solution:
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nTwo USB2.0 controller chips are in production with GSMC 0.18um 4M1P CMOS process
nA multi-media SOC ASIC with Tencilica cpu core to Silterra 0.16um process
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Netlist2GDS Service:
nA 500K gates design at 200MHZ, tapeout to Silterra 0.18um 6M1P cmos process
nA 1.5M gates design at 150MHZ, tapeout to GSMC 0.18um 6M1P cmos process
nShrink an ASIC from GSMC 0.15um to 0.13um process
nPlace and Route digital blocks using customer’s STD library
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Custom layout Service:
nLayout from schematic and tapeout serveral small analog chips
nCompact and recharacterize a 0.11um STD cell library
nCustom layout IP blocks from schematic for 0.18um, 90um, 65nm and 45nm TSMC process
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Success Stories 
