Our Place and Route Layout team delivers both standalone SOC and IP blocks from 0.18um to 40nm processes over the last ten years. We can work from either RTL or Netlist to GDS-II, based on customer’s requirements. Our design services include the followings:
    ●  Top level IC floor planning and layout
    ●  Multiple Voltage
    ●  Complex Clocking Scheme
    ●  DFT (including SCAN/BSD/MBIST and corresponding ATPG & Simulation)
    ●  Placement & Routing (including hierarchy Floor-plan & Special Route)
    ●  Physical Verification
    ●  Parasitic Extraction
    ●  Static Timing Analysis/ Advanced STA (AOCV,POCV)
    ●  Signal Integrity Analysis
    ●  Power Analysis
    ●  Formal Verification
    ●  IR drop/ EM Analysis
    ●  Tape-out & Job View